Static Random Access Memories (SRAMs) are one of the most popular ways to store data in electronic systems. Similarly, embedded SRAMs are a vital building block in integrated circuits. SRAMs are popular due to a relatively high speed, robust design and ease of integration. However, SRAMs, in general, occupy a significantly large portion of a chip's die area, making it an important block in terms of area, yield, reliability and power consumption. With increasing demand for highly integrated System on Chip designs, improving various aspects of embedded SRAMs has received significant interest.
A six-transistor (6T) SRAM cell is a popular configuration because of its high speed and robustness. This configuration, however, suffers from relatively high area due to the large number of transistors. Large cell area leads to longer bit-lines, word-lines and other control wires that run across an SRAM array. A long wire has relatively large capacitive load which either increases the dynamic power consumption or reduces the operational speed. Therefore, reducing the size of an SRAM cell is important and researchers have proposed several methods and techniques to do so.
Dynamic random access memory (DRAM) cells, which require less area than SRAMs have been developed. However, DRAMs require a special semiconductor manufacturing process and are, therefore, not easily integrated with conventional complementary metal-oxide-semiconductor (CMOS) digital circuits.
Conventional four-transistor (C4T) SRAMs have also been developed. Since SRAM can be implemented in a conventional CMOS technology, a C4T SRAM configuration it can easily be integrated into digital circuits. However, poor stability of the C4T cell makes its configuration less desirable.
Accordingly, it is an object of the present invention to obviate or mitigate at least some of the above-mentioned disadvantages.